The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
For example, as the size of a feature is scaled down, a resolution of an optical lithography system is improved. However, a depth of focus (DOF) is decreased as a consequence of improved resolution. In many cases, the DOF is barely sufficient to support a resist film thickness, wafer flatness, and planarization tolerance of the IC device, focusing and leveling errors of the optical lithography system. Accordingly, what is needed is a method to improve the DOF of the optical lithography system.